1. Field of the Invention
The present invention generally relates to a method of manufacturing a 3-D vertical memory, and more particularly, to a method of manufacturing a 3-D vertical memory with U-shaped pipe channel structures.
2. Description of the Prior Art
In the conventional planar type memory structure field, since the components of a memory cell, such as the gate, the source and the drain, are all formed on the same plane, the area of a memory cell (generally 4F2, wherein F is the exposure limitation of the photolithographic tool) can only be scaled down by changing the critical dimension (CD) in the exposure process performed by photolithographic tool. For this kind of planar type memory design, it is impossible to significantly increase the number of memory cells in a memory array. Especially, the current memory processes have regular critical dimensions configured to be smaller than 40 nm. The available photolithographic tool with such exposure capability is exorbitantly expensive. The cost of research and development for this kind of semiconductor processes is accordingly too costly. In order to respond the aforementioned cost issue, many novel processes based on using common, existing photolithographic tools have been developed in the industry in order to manufacture devices or circuit structures with more compact architectures. However, those proposed processes are mostly complicated and are showing lower product yields. Moreover, for planar type memory structures, serious crosstalk problem may occur between adjacent memory units when the size is scaled down to a threshold level. These crosstalk phenomena may deteriorate the original electrical performances of the memory device. Therefore, the aforementioned difficulties are no doubt hindering the scaling-down progression of the memory sizes.
In the light of the limitation in the size scale-down for current planar type memory structures, the development of three dimension (3-D) vertical stacked memory architectures has been initiated in the industry in order to significantly increase the number of memory cells in one memory array. In the so-called 3-D vertical memory structures, the control gates of the memory device are vertically stacked, so that the necessary area for the memory cell may be significantly reduced. For example, the area of a memory cell in this kind of 3-D architecture is generally 6F2/N, wherein F is the exposure limitation of the used photolithographic tool, and N is the number of stacked control gates. Most important, the existing common process tools are well-adapted to perform the process of manufacturing this kind of 3-D vertical memory structures, thus there is no need to invest huge cost in purchasing expensive process tools or developing brand-new technologies.
Currently, there are two developed 3D vertical memory candidates in the industry, one is the pipe-shaped bit cost scalable (P-BiCS) technology, and the other one is the terabit cell array transistor (TCAT) technology. Both of these two memory technologies have their own advantages and disadvantages in nature.
As far as P-BiCS technology is concerned, please refer to the article in reference “2009 Symposium on VLSI Technology Digest of Technical Papers”, section 7-1, entitled “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”. As shown in FIG. 1 and FIG. 2 of this article, the storage signal is transmitted from the upper source lines (SL) to the topmost bit lines (BL) through a U-shaped pipe connection (PC). The U-shaped pipe connection is designed to run through a plurality of stacked control gates (CG) and cooperatively complete the operation of data storage. The advantage of the P-BiCS technology is that the source lines are disposed on the upper portion of the memory structure, thus the source line may be made of metal materials with lower resistance so as to improve the electrical performances. However, in current P-BiCS process, the control gate portion can not be made by using metal materials, thus the word line (WL) in this structure will have higher RC values, which may influence the electrical performances of memory device and also make it difficult to perform the contact process for the word lines in following processes.
On the other hand, as far as the TCAT technology is concerned, please refer to the article in reference “2009 Symposium on VLSI Technology Digest of Technical Papers”, section 10A-1, entitled “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effect NAND Flash memory devices and SSD (Solid State Drive)”. As shown in FIG. 1 and FIG. 2 in this article, the storage signal is designed to be transmitted upwardly from the bottom source select line (SSL) to the upper bit line through a plurality stacked control gate structures. The advantage of the TCAT technology is that the control gate may be made of metal materials, so the word lines in this structure may have lower RC values. However, the disadvantage of the TCAT technology is that the source line is formed on the lower Poly-Si layer, thus the source line cannot be made out of metal materials and will have high resistances, which may influence the electrical performances of memory device.
Accordingly, both of the aforementioned two 3-D vertical stacked memory technologies have their drawbacks in their structure or process nature. How to improve these technologies and overcome the existing drawbacks is still one of essential topic for those of ordinarily skilled in the art.